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CD4015BT
Data Sheet July 1999 File Number
4621.1
CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output
Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. CD4015BT consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one CD4015BT, or to more than 8 stages using additional CD4015BT's is possible.
Features
* QML Class T, Per MIL-PRF-38535 * Radiation Performance - Gamma Dose () 1 x 105 RAD(Si) - SEP Effective LET > 75 MEV/gm/cm2 * Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V * Fully Static Operation * 8 Master-Slave Flip-Flops Plus Input and Output Buffering * 100% Tested For Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings * Standardized Symmetrical Output Characteristics
Pinouts
CD4015BT (SBDIP), CDIP2-T16 TOP VIEW
CLOCK B 1 Q4B 2 Q3A 3 Q2A 4 Q1A 5 RESET A 6 DATA A 7 VSS 8 16 VDD 15 DATA B 14 RESET B 13 Q1B 12 Q2B 11 Q3B 10 Q4A 9 CLOCK A
Specifications
Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the CD4015BT are contained in SMD 5962-96624. A "hot-link" is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil's Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp
CLOCK B
CD4015BT (FLATPACK), CDFP4-F16 TOP VIEW
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD DATA B RESET B Q1B Q2B Q3B Q4A CLOCK A
Ordering Information
ORDERING NUMBER 5962R9662401TEC 5962R9662401TXC PART NUMBER CD4015BDTR CD4015BKTR TEMP. RANGE (oC) -55 to 125 -55 to 125
Q4B Q3A Q2A Q1A RESET A DATA A VSS
NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
CD4015BT Functional Diagram
VDD 16 DATA A CLOCK A RESET A 7 9 6 4 STAGE 5 4 3 10 DATA B CLOCK B RESET B 15 1 14 4 STAGE 13 12 Q2B 11 Q3B 2 Q4B 8 VSS Q1A Q2A Q3A Q4A Q1B
Logic Diagram
Q1 13 (5) Q2 12 (4) Q3 11 (3) Q4 2 (10)
DATA
15 (7)
D
Q
D
Q
D
Q
D
Q
CLOCK
1 (9)
CL R
Q
CL R
Q
CL R
Q
CL R
Q
CL RESET
14 (6) DQ VDD CL Q R
CL p D n CL CL p VSS n
CL p n
Q
CL
CL
Q CL
CL p n R CL
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION NETWORK CL
TRUTH TABLE CL D 0 1 X X X R 0 0 0 1 Q1 0 1 Q1 0 Qn Qn-1 Qn-1 Qn 0 (No Change)
X = Don't care Case
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CD4015BT Die Characteristics
DIE DIMENSIONS: (2032m x 2489m x 533m 25.4m) 80 x 98 x 21mils 1mil METALLIZATION: Type: Al Thickness: 12.5kA 1.5kA SUBSTRATE POTENTIAL: Leave Floating or Tie to VDD; Bond Pad #16 (VDD) First BACKSIDE FINISH: Silicon PASSIVATION: Type: Phosphorus Doped Silox (SiO2) Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 60 PROCESS: Bulk CMOS
Metallization Mask Layout
CD4015BT
80mils
1 3 2 16 15
4
14
5
98mils
13
6
12
7
8
9
10
11
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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